1. Field of the Invention
The present invention generally relates to receiver circuits that synchronize the receiver side with the transmitter side, and particularly relates to a symbol timing recovery circuit that recovers the symbol timing on the receiver side.
2. Description of the Related Art
In high-speed serial communications, provision is made to avoid the transmission of a clock signal as a separate signal from communication data, thereby reducing the number of communication lines. On the data receiving side, the communication data transmitted from the transmitter side need to be properly received. To this end, a symbol timing recovery circuit is employed, for example, to control the phase of the received signal for synchronization with the clock on the data receiving side.
FIG. 1 is a drawing showing an example of the configuration of a related-art symbol timing recovery circuit. This symbol timing recovery circuit is disclosed in Japanese Patent Application Publication No. 2000-101659. The symbol timing recovery circuit of FIG. 1 includes a clock control circuit 10, flip-flops (F/F) 11 and 12, a digital filter 13, a phase comparator 14, a loop filter 15, an NCO (numerical controlled oscillator) 16, and a tap coefficient computing unit 17.
The flip-flop 11 receives data DATA, which is sampled at such sufficiently high frequency that all the signal frequency components of the received signal are below the Nyquist frequency. The flip-flop 11 latches the received data DATA by use of a clock signal CLK1, and outputs the latched data. The clock signal CLK1 has a frequency more than twice as high as the symbol rate of the received data DATA. Accordingly, the output of the flip-flop 11 is equivalent to received data that is made by sampling the received signal at the frequency of the clock signal CLK1.
The digital filter 13 delays the output of the flip-flop 11 in response to the tap coefficients provided therein, thereby generating delayed received data. The flip-flop 12 latches the delayed received data by use of a clock signal CLK2, and outputs the latched data. The clock signal CLK2 is obtained by decimating the clock pulses of the clock signal CLK1 by use of the clock control circuit 10. Here, the control is such that the frequency after the decimation is equal to twice the symbol rate of the received data DATA. The symbol rate of the received data DATA may be 18 MHz, and the frequency of the clock signal CLK1 may be 48 MHz, for example. In this case, the clock control circuit 10 decimates (discards) one in every four clock pulses of the clock signal CLK1, thereby generating the 36-MHz clock signal CLK2. With this provision, the received data that is sampled at twice the symbol rate (18 MHz×2=36 MHz) is obtained. Such received data is comprised of the data identifying points and zero-crossing points of the received signal appearing alternately.
In the operation described above, the clock decimation by the clock control circuit 10 serves to match the clock frequency on the receiver side with the symbol rate of the received signal. Further, the delay imposed by the digital filter 13 serves to adjust the phase of the received signal for synchronization with the clock signal on the receiver side. In such delaying, specifically, a filtering process is performed by use of the coefficients responsive to the timing difference between the actual sample points and the data identifying points or zero-crossing points. As a result, the samples (i.e., outputs of the flip-flop 11) that are taken at the timing deviating from the data identifying points or zero-crossing points are interpolated to remove a phase displacement (timing displacement), thereby computing values sampled at the data identifying points or zero-crossing points.
The decimation by the clock control circuit 10 and the filtering process by the digital filter 13 are controlled based on the feedback control using the output of the flip-flop 12. This feedback control is performed such that the output of the flip-flop 12 resulting from the filtering process by the digital filter 13 coincide with the data identifying points or zero-crossing points. Specifically, the phase comparator 14 uses, among the output data of the flip-flop 12, the value of the data supposed to be at a zero-crossing point and the values of the data supposed to be at the preceding and following data identifying points, and computes a deviation from the conditions that are supposed to be satisfied by the values of the zero-crossing points and the values of the data identifying points. This computed value represents a phase difference between the output of the flip-flop 12 and the zero-crossing points or data identifying points.
The value indicative of a phase difference that is output from the phase comparator 14 is integrated by the loop filter 15. The NCO 16 oscillates at the frequency responsive to the value indicated by the output of the loop filter 15. For example, the larger the output of the loop filter 15, the higher the oscillating frequency of the NCO 16 is. The smaller the output of the loop filter 15, the lower the oscillating frequency of the NCO 16 is. The oscillating signal of the NCO 16 has a sawtooth waveform. In response to the signal value of this sawtooth waveform, the tap coefficient computing unit 17 computes filter coefficients for provision to the digital filter 13.
When there is a difference between the frequency of the clock signal CLK1 and twice the frequency of the symbol rate, a timing difference between the sample points of the output of the flip-flop 11 and the data identifying points or zero-crossing points gradually increases, and then gradually decreases. Such timing difference gradually increases again, and then gradually decreases. Such actions are repeated. Here, changes in the value of the sawtooth waveform match these changes in the timing difference. The process performed by the digital filter 13 cancels out this timing difference.
When there is a difference between the frequency of the clock signal CLK1 and twice the frequency of the symbol rate, there is a need to downsample the number of samples of the output of the flip-flop 11 since the number of these samples is larger than the number of the data identifying points and the zero-crossing points. Such a need arises even through the digital filter 13 cancels out the timing difference. The clock control circuit 10 decimates the clock pulses at the timing corresponding to a falling edge of the sawtooth waveform output from the NCO 16, thereby achieving a desired decimation.
FIG. 2 is a drawing for explaining the decimation of the clock signal by the clock control circuit 10. As shown in FIG. 2, one of the clock pulses of the clock signal CLK1 is decimated at the timing corresponding to a falling edge of the sawtooth signal output from the NCO 16, thereby generating the clock signal CLK2.
In the symbol timing recovery circuit as shown in FIG. 1, the operating performance extremely drops when the rate of clock pulse decimation is a reciprocal of an integer number such as ½ (decimation of one in every two) or ⅓ (decimation of one in every three).
FIG. 3 is a drawing for explaining the problem associated with the decimation of the clock signal CLK1 at a rate of ½. When the clock signal CLK1 is decimated at a rate of ½ under ideal conditions, clock pulses are discarded at the timing corresponding to the falling edges of a sawtooth waveform shown as NCO2 having half the cycle of the clock signal CLK1. Consequently, a signal like the clock signal CLK2 having clock pulses evenly distributed is obtained after the balanced decimation of clock pulses. In actual circuitry, however, the falling edges of the output signal of the NCO 16 may have fluctuating timing due to the effect of jitter from the loop filter 15 to the NCO 16 shown in FIG. 1, for example. In such a case, a signal waveform as shown as NCO3 is obtained. When the clock pulses are decimated at the timing corresponding to the falling edges of such sawtooth signal (a clock pulse immediately following each falling edge is decimated), the resulting waveform will be like a clock signal CLK3 illustrated at the bottom.
The clock signal CLK3 has the desired decimation ratio (decimation rate) that is equal to ½. However, the distribution of clock pulses is extremely uneven. The intended operation is to perform a latch operation of the flip-flop 12 of FIG. 1 by use of a clock signal such as the clock signal CLK2 shown in FIG. 3, thereby generating data in which the values of data identifying points and the values of zero-crossing points appear alternately. In actuality, however, an irregular clock signal such as the clock signal CLK3 shown in FIG. 3 is used to perform a latch operation of the flip-flop 12 shown in FIG. 1. This cannot achieve such proper decimation that the values of data identifying points and the values of zero-crossing points are properly left. As a result, the recovery of the received signal becomes inaccurate, causing degradation in the signal reception performance.
FIG. 4 is a drawing showing the relationship between decimation rates and error rates obtained by simulation. In FIG. 4, the vertical axis represents BER (bit error rate), and the horizontal axis represents the ratio of NCO revolution. Here, a NCO revolution ratio of 2.000 corresponds to a decimation rate of ½. The NCO revolution ratio and the decimation rate are in a reciprocal relationship.
As shown in FIG. 4, degradation in the performance is significant around an NCO revolution ratio of 2 (decimation rate of ½). Further, degradation in the performance increases at the points where the decimation rate is a reciprocal of an integer number such as the points corresponding to an NCO revolution ratio of 3 and 4 (decimation rate of ⅓ and ¼). As the NCO revolution ratio increases from 3, to 4, 5, and so on, a ratio of the number of decimated samples to the total number of sample points decreases. As a result, the effect on the BER performance of the fluctuating decimation timing caused by the fluctuation in the sawtooth waveform decreases.
As a method for avoiding the problem of performance degradation occurring with a decimation rate equal to a reciprocal of an integer number, a plurality of sampling clock may be provided, and are used selectively depending on the symbol rate, thereby avoiding a situation where the decimation ratio becomes a reciprocal of an integer number. Such a configuration using a plurality of clocks, however, gives rise to a problem that the circuit becomes complex and the circuit size increases. Further, it is difficult to switch clocks seamlessly, thereby giving rise to a problem that the symbol rate cannot be easily changed.
Accordingly, there is a need for a timing recovery circuit and a decimated clock generating method that can prevent the performance degradation associated with the decimation of a clock signal.